1. Field of the Invention
The disclosure relates in general to a three-dimensional (3D) memory structure, and more particularly to a structure of ECC spare bits in 3D memory.
2. Description of the Related Art
In those years, the configurations of semiconductor devices have been refined, and the capacity of semiconductor memories has been increased. Particularly, manufactures have been looking for the developments or techniques combination for stacking multiple planes of memory cells, so as to achieve greater storage capacity. For example, several types of multi-layer stackable thin-film transistor (TFT) NAND-type flash memory structures have been proposed. Thus, the size of the semiconductor device with large capacity is reduced due to the stacked three-dimensional (3D) memory structure.
The development of semiconductor devices has generally followed Moore's, and the device size has been reduced to half every 1˜2 years in these years. However, the accepted defect size shrinks to half at the same time. This results in the difficulty during production. For non-violate memory (NVM), moreover, multi-level or even triple-level cell design further reduces the process/product window.
ECC (Error Checking and correcting) and repair function are the most promising solution. However, they are not free. Extra ECC bits are necessary to store the information for data correction. For performing the ECC and repair function, the more error bits to be corrected, the more spare area has to be reserved for ECC bits. Typical two-dimensional semiconductor structure need extra area for ECC and repair function. For example, to perform ECC/repair function in a 1 KB page size with the BCH model for a 2D semiconductor structure, about 4%˜4.2% extra area for spare bits are required to correct the error up to 24 bits. As to 2×nm node MLC NAND structure, 64-bit ECC is need, and the forecasted spare area for performing 64-bit ECC will be 11.2%, which is roughly the same as cost increase of 11.2%. Thus, the more error bits to be corrected, the more spare area of ECC bits to be reserved and the more expansive of the product.
Regarding to SSD (solid state drive), some analyses comment that over 100-bit ECC would be needed, equivalent to 17.5% penalty in area (17.5% of extra cost), to guarantee the better reliability of device.
FIG. 1 depicts a typical three-dimensional (3D) memory with ECC spare. The 3D memory structure 1 of FIG. 1 has 4 planes/stacking memory layers 101-104 on the substrate 10, wherein the ECC spare portion 12 in every stacking memory layer contains ECC bits for correcting/repairing the information data stored in the portion 11. The typical three-dimensional (3D) memory structure have the same issue as the two-dimensional (2D) memory structure, extra area in each plane (4 planes/stacking memory layers shown in FIG. 1) is need for ECC/repair. For 3D memory, more spare area for performing ECC/repair function is required supposedly for the concern of uniformity of TFT devices.
Generally, it is easier to design a 3D memory with 2N stacking memory layers with ECC/repair spare bits, (for example, 4 planes/stacking memory layers 101˜104 on the substrate 10 as shown in FIG. 1 are increased to 8 planes/stacking memory layers) since cost drop to half while a number of the stacking memory layers are doubled. Although it is possible to design a 3D memory with non-2N stacking memory layers with ECC/repair spare bits, it may need some extra effort on the structural design and may increase cost on periphery manufacture. FIG. 2 depicts another typical three-dimensional (3D) memory with ECC spare. The 3D memory 1 of FIG. 1 has 4 stacking memory layers (i.e. 2N stacking memory layers), and the 3D memory 2 of FIG. 2 has 6 stacking memory layers 101˜106 (i.e. non-2N stacking memory layers). It is estimated that the complex design of 3D memory of FIG. 2 would increase the periphery manufacturing cost of about 10% although the array manufacturing cost drop is about 33%.
Besides the manufacturing techniques (such as etching defects) and the reliability of TFT performance to be improved, it is also desirable to develop a three-dimensional flash memory structure with larger number of multiple planes being stacked to achieve greater storage capacity using an improved way of ECC correction without increasing the manufacturing cost, even decreasing the cost.